BIST Architecture for Magnetic Memories
Keywords:Memory BIST, Memory testing, Magnetic memory, Emerging memory, System on Chip
Magnetic random-access memory (MRAM) is one of the emerging memory technologies, which can be considered as the next universal memory because of its good parameters. Nevertheless, this type of memory is not guaranteed from defects and it is very important to understand the fault typology and develop a test solution that addresses these faults. In this paper a Built-in Self-Test (BIST) solution is presented,which is specifically tailored for MRAMs and efficiently deals with MRAM specific faults.
T. J. Chang et al. “A 5-nm 135-Mb SRAM in EUV and high-mobility channel FinFET technology with metal coupling and charge-sharing write-assist circuitry schemes for high-density and low-VMIN applications”, in IEEE Int. Solid-State Circuits Conf. (ISSCC), Dig. Tech. Papers, pp. 238-239, Dec. 2020.
J. Baek et al. “A sub-0.85V, 6.4Gbp/s/pin TX-interleaved transceiver with fast wake-up time using 2-step charging control and VOH calibration in 20nm DRAM process”, in Symposium on VLSI Circuits Digest of Technical Papers, pp. 430-431, June 2018.
J. Lee, “A 1.8 Gb/s/pin 16Tb NAND flash memory multi-chip package with F-chipof toggle 4.0 specification for high performance and high capacity storage systems”, in IEEE Symposium on VLSI Circuits, pp. 190-191, June 2020.
S.M. Nair et al. “Defect injection, fault modeling and test algorithm generation methodology for STT-MRAM”, IEEE International Test Conference (ITC), pp. 1-10,2018.
I. Yoon, A. Chintaluri and A. Raychowdhury, "EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays", IEEE International Test Conference (ITC), pp. 1-10, 2016.C. Suetal, "Write disturbance modeling and testing for MRAM", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3, pp. 277-288, 2008.