An Efficient Method for Generation of March Tests Based on Formulas
Abstract
A general method for generation of minimal March tests to detect or diagnose any subclass of simple static or dynamic faults in Static RAMs is described. The proposed method is shown to generate all possible March tests satisfying certain necessary conditions for detection of faults. A correspondence between March tests and natural numbers is established that allows construct a formula that enables generation of all March tests detecting certain faults. As an example, the method is applied for construction of new minimal March tests for detection of several subclasses of three-operation dynamic faults. The method can be generalized for detection/diagnosis of any subset of static or dynamic faults.
References
A.J. van de Goor, Testing semiconductor memories: Theory and Practice, John Wiley & Sons, 1991.
A.J. van de Goor, B. Smit, "The automatic generation of march tests", IEEE International Workshop Memory Technology Design and Testing, pp. 131-136, 1993.
K. Zarrineh, S.J. Upadhyaya, and S. Chakravarty, "A new frame work for generating optimal march tests for memory arrays", Proc. Int. Conf. (ITC), pp. 73-82, 1998.
A. Benso, S. Di Carlo, G. Di Natale, P. Prineto, "An optimal algorithm for the automatic generation of march tests", DATE 2002, IEEE Design, Automation and Test in Europe Conference and Exhibition, pp. 938-939, 2002.
S.M. Al-Harbi, S.K. Gupta, "An efficient methodology for generating optimal and uniform march tests", IEEE VLSI Test Symposium, pp. 231-237, 2001.
C.-F. Wu, C.-T. Huang, and C.-W. Wu, "RAMSES: a fast memory fault simulator", Proc. Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, pp. 165-173, Nov. 1999.
J.-F. Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "March-based RAM diagnostic algorithms for stuck-at and coupling faults", Proc. IEEE ITC, pp. 758-767, 2001.
T. Gyonjyan, V.A. Vardanian, "An efficient algorithm for generating minimal march tests for fault detection and diagnosis in static random access memories", International Design and Test Workshop, Dubai, pp. 19-20, 2006.
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto, "Automatic march tests generation for static and dynamic faults in SRAMs",
G. Harutunyan, V.A. Vardanian, Y. Zorian, "Minimal march tests for dynamic faults in random access memories", Journal of Electronic Testing: Theory and Applications, Vol. 23, Number 1 ,pp. 55-74, 2007.
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian, "Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 μm and 90 nm technologies", Design Automation Conference, pp. 857-862, 2005.
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan, "Dynamic read destructive ault in embedded-SRAMs: analysis and march test solutions", Proc. IEEE European Test Symposium, 2004.
S. Hamdioui, A.J. van de Goor, M. Rodgers, "March SS: a test for all static simple faults", Records of IEEE Int. Workshop MTDT, pp. 95-100, 2002.
S. Hamdioui, A.J. van de Goor, M. Rodgers, "Linked faults in random access memories: concept, fault models, test algorithms, and industrial results", IEEE Trans. CAD, vol. 23, No. 5, pp. 737-756, 2004.
G. Harutunyan, V.A. Vardanian, Y. Zorian, "Minimal march tests for unlinked static faults in random access memories", Proc. 23rd IEEE VLSI Test Symposium, Palm Springs, CA, USA, pp. 53-59, 2005.
A.J. van de Goor, Z. Al-Ars, "Functional memory faults a formal notation and a taxonomy", Proc. IEEE VLSI Test Symposium, Montreal, Canada, pp. 281-290, 2000.
Aho, Sethi, Ullman, Compilers: Principles, Techniques, and Tools, Addison-Wesley, ISBN 0-201-10088-6, 1986.
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